1. Field of the Invention
This invention relates to an analog-to-digital converter, such as used for digital voltmeters, digital ohmmeters, and the like; and more particularly, to improvements in the conversion accuracy and resolution of a double integrating analog-to-digital converter.
2. Description of the Prior Art
There are various conventional analog-to-digital (known as AD) converters which are enhanced to obtain high accuracy and high resolution, such as the triple integrating AD converter. FIG. 5 depicts one example of a triple integral AD converter; and FIGS. 6(A)-6(H) are time charts useful in explaining the operation thereof. In FIGS. 6(A)-6(H), in the initial state (i.e. the state until t1) switches S1, S2, and S3 (of FIG. 5) are switched OFF, a reset switch SR is switched ON and an integrator 14 is reset. Then, switch S1 is switched ON for a predetermined period of time Ti (which is from time t1 to time t2) to integrate a voltage to be measured -Vi. The output of integrator 14 increases in the positive direction as shown in FIG. 6(A). Time period Ti is controlled by counting clock pulses using a counting and switching control circuit 22. Upon reaching time t2, switch S1 is switched OFF and switch S2 is switched ON to integrate a first reference voltage +Vr1 having a reversed polarity to voltage -Vi to be measured. During this period, the time is measured utilizing high speed clock pulses. When the output of integrator 14 reaches a first detection level +VC, it is detected by first level detector 19 as shown in FIG. 6(H) and switch S2 is switched OFF and switch S3 is switched ON in synchronism with the clock pulses.
Thus, a second reference voltage +Vr2, which is lower than first reference voltage +Vr1, is supplied to integrator 14 to be integrated. The output of integrator 14 decreases toward the initial value 0 V with a gentle slope. During period Tr2 (from t3 to t4), the time is measured by low speed clock pulses. When the output of integrator 14 reaches 0 V, it is detected by a second level detector 20 and switch S3 is switched OFF, and reset switch SR is switched ON to end the AD conversion.
Since the amount of charge accumulated during the period t1 to t2 and the amount of charge released durign the period t2 to t4 (i.e. Tr1+Tr2) are equal, the digital value of the voltage to be measured can be found by taking the weighted sum of the number of pulses in period Tr1 and those in period Tr2.
In short, this triple integrating AD converter of FIG. 5 is a system which divides integrating periods by the reference voltages into integration of the first reference voltage and that of the second reference voltage and to integrate roughly in the first half and finely in the second half by making the slope gentle.
However, this conventional system has various disadvantages. For example, it requires two types of clock pulses, two different types of reference voltages having different voltages, and another comparator and comparison level for changing the slope of integration in addition to the comparator for detecting the crossing of the reference level.